Integrated circuit and interconnect, and method of fabricating same

ABSTRACT

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

TECHNICAL FIELD

The disclosure relates generally to integrated circuits and methods offabricating the same, and more particularly, to integrated circuitshaving interconnects such as high performance inductors.

BACKGROUND

Integrated circuit interconnects, and particularly, high performanceinductors are used for most types of radio frequency circuits and aretypically fabricated having thick metal wires such as copper oraluminum. Traditionally, the metal wires are formed using electrolyticplating processes in conjunction with photoresist masking and stripping,and removing a seed layer later on.

SUMMARY

An aspect of the present invention relates to an integrated circuitcomprising: at least one trench within a dielectric layer disposed on asubstrate, the trench conformally coated with a liner and seed layer;and an interconnect within the trench, the interconnect including a hardmask on sidewalls of the interconnect.

A second aspect of the present invention relates to a method offabricating an interconnect in an integrated circuit, the methodcomprising: conformally coating a trench with a liner and seed layer,the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer; masking andpatterning the trench to expose the hard mask; removing exposed areas ofthe hard mask to expose areas of the liner and seed layer; electrolyticmetal plating the exposed areas of the liner and seed layer to form aninterconnect; and planarizing the interconnect with a top surface of thetrench.

A third aspect of the present invention relates to an inductorcomprising: a core conductor including a top surface, a bottom surface,and sidewalls within a trench, the trench being within a dielectriclayer on a substrate, and having a liner and seed layer on a bottom andsidewalls of the trench; and a hard mask on the sidewalls of the coreconductor.

A fourth aspect of the present invention relates to a method offabricating an inductor, the method comprising: conformally coating atrench with a liner and seed layer, the trench being within a dielectriclayer on a substrate; depositing a hard mask on the liner and seedlayer; masking and patterning the trench to expose the hard mask;removing exposed areas of the hard mask to expose areas of the liner andseed layer; electrolytic metal plating the exposed areas of the linerand seed layer to form a core conductor; and planarizing the coreconductor, the hard mask, the liner and seed layer with a top surface ofthe trench.

The illustrative aspects of the present invention are designed to solvethe problems herein described and/or other problems not discussed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings that depict various embodiments of the invention, in which:

FIG. 1 depicts an embodiment of an integrated circuit including at leastone interconnect, in accordance with the present invention;

FIGS. 2A-2H depicts steps of an embodiment of a method for fabricatingan interconnect in an integrated circuit, in accordance with the presentinvention;

FIG. 3 depicts an embodiment of an inductor, in accordance with thepresent invention; and

FIGS. 4A-4H depicts steps of an embodiment of a method for fabricatingan inductor, in accordance with the present invention.

It is noted that the drawings of the invention are not to scale. Thedrawings are intended to depict only typical aspects of the invention,and therefore should not be considered as limiting the scope of theinvention. In the drawings, like numbering represents like elementsbetween the drawings.

DETAILED DESCRIPTION

In order to achieve high performance (high quality factor) integratedcircuits (IC) and IC interconnects employing thick copper wires, and inparticular, copper inductors, fabrication techniques such asthrough-plating are commonly used. It has been discovered that imagesize tolerance and overlay associated with through-plating techniquesare not adequate for fabrication of high performance interconnects suchas inductors. Alternatively, selective plating fabrication techniqueshave been used to form interconnects. However, copper seed layercorrosion can occur during chemical-mechanical polishing of the layerand cross-wafer plating uniformity associated with selective platingfabrication remains a concern using selective plating fabricationtechniques.

An embodiment of an integrated circuit (IC) including at least oneinterconnect is presented in FIG. 1, in accordance with the presentinvention. Referring to FIG. 1, an IC 10 is shown. IC 10 represents aminiaturized electronic circuit constructed of individual semiconductordevices, as well as passive components, etc. bonded to a substrate orcircuit board. IC 10 may represent any conventional IC known in the artand may comprise any conventional IC components known in the art. A blowup 15 represents an expanded, cross-sectional view of a selected area 17of IC 10 so that selected area 17 may be seen and described moreclearly. Blow up 15 shows a trench 20, a dielectric layer 25, asubstrate 30, a liner and seed layer 35, an interconnect 40, and a hardmask 45 of IC 10. Trench 20 is within dielectric layer 25 whereindielectric layer 25 is disposed on substrate 30. Trench 20 may beapproximately 5 microns (μm) to approximately 150 μm wide andapproximately 5 μm to approximately 20 μm deep.

Substrate 30 is a semiconductor substrate that may comprise but is notlimited to silicon, germanium, silicon germanium, silicon carbide, andthose consisting essentially of one or more Group III-V compoundsemiconductors having a composition defined by the formulaAl_(X1)Ga_(X2)In_(X3)As_(Y1)P_(Y2)N_(Y3)Sb_(Y4), where X1, X2, X3, Y1,Y2, Y3, and Y4 represent relative proportions, each greater than orequal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relativemole quantity). Semiconductor substrate 30 may also comprise Group II-VIcompound semiconductors having a compositionZn_(A1)Cd_(A2)Se_(B1)Te_(B2), where A1, A2, B1, and B2 are relativeproportions each greater than or equal to zero and A1+A2+B1+B2=1 (1being a total mole quantity).

Dielectric layer 25 may be approximately 5 μm to approximately 20 μmthick. Dielectric layer 25 may be a material such as but not limited tosilicon oxide (SiO₂), silicon nitride (Si₃N₄), hafnium oxide (HfO₂),hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON),zirconium oxide (ZrO₂), zirconium silicon oxide (ZrSiO), zirconiumsilicon oxynitride (ZrSiON), aluminum oxide (Al₂O₃), titanium oxide(Ti₂O₅), tantalum oxide (Ta₂O₅), hydrogen silsesquioxane polymer (HSQ),methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer)manufactured by Dow Chemical, Midland, Mich.; Black Diamond™[SiO_(x)(CH₃)₃] manufactured by Applied Materials, Santa Clara, Calif.;fluorinated tetraethylorthosilicate (FTEOS), and fluorinated siliconglass (FSG). In an embodiment, dielectric layer 25 may comprise FSG oran organic material, for example, a polyimide.

Dielectric layer 25 may also comprise multiple dielectric layers, forexample, a first low-k (dielectric constant) layer and a seconddielectric layer such as Si₃N₄ or SiO₂. The second dielectric layer mayhave a higher k dielectric constant value than the first low-kdielectric layer. Low-k dielectric layers include materials having arelative permittivity value of 4 or less, examples of which include butare not limited to HSQ, MSQ, SiLK™, Black Diamond™, FTEOS, and FSG.

Trench 20 may include a conformal coating of liner and seed layer 35.Liner and seed layer 35 may be approximately 500 Å to approximately3,000 Å thick. The liner component of layer 35 may comprise tantalum(Ta), tantalum nitride (TaN), tantalum-aluminum nitride (TaAlN),tantalum silicide (TaSi₂), titanium (Ti), titanium nitride (TiN),titanium-silicon nitride (TiSiN), or tungsten (W). The liner componentmay be a layer approximately 100 Å to approximately 500 Å thick. Theseed component of layer 35 may be, for example, a copper seed layerdisposed on the liner layer and may be approximately 400 Å toapproximately 2,000 Å thick. In an embodiment, the liner component oflayer 35 is in contact with trench 20 and substrate 30, and the seedcomponent overlays the liner component.

Interconnect 40 is located within trench 20 and may include a hard mask45 on sidewalls 42 of interconnect 40. Interconnect 40 may comprisecopper, silver, and/or gold, and for example, may be used as an inductoror a transmission line. Interconnect 40 may be approximately 5 μm toapproximately 150 μm wide. Hard mask 45 may be an anti-seedingconductive material or a dielectric material. The anti-seedingconductive material may be selected from the group consisting of TiN,Ta, and TaN. The dielectric material may be selected from the groupconsisting of silicon nitride (Si₃N₄), silicon carbide (SiC), andaluminum oxide (Al₂O₃).

An embodiment of steps of a method for fabricating an interconnect in anintegrated circuit are shown in FIGS. 2A-2H. Referring to FIG. 2A, asubstrate 30 comprising silicon, silicon-on-insulator, silicongermanium, or gallium arsenide is provided. Substrate 30 may include anyconstruction comprising semiconductor material, including but notlimited to bulk semi-conductive materials such as a semiconductor wafer(either alone or in assemblies comprising other materials thereon, forexample, an integrated circuit).

Substrate 30 may already have a dielectric layer 25 deposited thereon.Dielectric layer 25 may include silicon oxide, FSG, or an organicmaterial, for example, polyimide. Alternatively, dielectric layer 25 maybe deposited on substrate 30 using any now known or later developedtechniques appropriate for the material to be deposited including butnot limited to, for example: chemical vapor deposition (CVD),low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphereCVD (SACVD) and high density plasma CVD (HDPCVD).

A trench 20 is etched into dielectric layer 25. This may be accomplishedby applying a layer of photoresist on dielectric layer 25, performing aphotolithographic process, and performing a reactive ion etch (RIE)process selective to etch, for example, silicon oxide, to define trench20 in dielectric layer 25.

Referring to FIG. 2B, trench 20 is conformally coated with a liner andseed layer 35. The liner component of layer 35 deposited may be Ta andmay be approximately 100 Å to approximately 1,000 Å thick. The seedcomponent of layer 35 may be copper and may be approximately 400 Å toapproximately 2,000 Å thick. The aforementioned may be formed by, forexample, PVD. Liner and seed layer 35 may conformally coat the bottomand side walls of trench 20, and a top surface of dielectric layer 25.

Referring to FIG. 2C, a hard mask 45 may be deposited on liner and seedlayer 35 via conventional CVD or PVD processes known in the art.Alternatively, hard mask 45 may be deposited using any now known orlater developed techniques appropriate for the material to be depositedincluding but not limited to, for example: low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), ultra-high vacuum CVD (UHVCVD), limitedreaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, and atomic layer deposition (ALD). Hard mask 45 maycomprise TiN and may be approximately 300 Å to approximately 1,000 Åthick throughout the entire layer. In an embodiment, hard mask 45 may beapproximately 400 Å thick.

Referring to FIG. 2D, trench 20 may be masked with a photoresist layer50 and may be patterned to expose the area of hard mask 45 that coatsthe bottom of trench 20. Photoresist layer 50 may be approximately 8 μmto approximately 50 μm thick. In one embodiment, photoresist layer 50may be approximately 10 μm. Photoresist materials used for masking andpatterning, and methods of performing the same are known in the art.

Referring to FIG. 2E, a reactive ion etch (RIE) may then be performed topartially etch the area of hard mask 45 that coats the bottom of trench20. The thickness of the area partially etched may be reduced fromapproximately 400 Å to approximately 100 Å. Photoresist layer 50 maythen be subsequently stripped.

Referring to FIG. 2F, a blanket RIE may be performed etching theremaining area of hard mask 45 that coats the bottom of trench 20 andthe areas of hard mask 45 coating liner and seed layer 35 on dielectriclayer 25. The remaining area of hard mask 45 may be etched away exposingthe copper seed component of layer 35, and the areas coating liner andseed layer 35 may be etched to approximately 300 Å.

Referring to FIG. 2G, interconnect 40 may be formed from liner and seedlayer 35 by performing an electrolytic metal plating process to filltrench 20. The process may be performed with a current density ofapproximately 1 A/cm² to approximately 20 A/cm² using a plating solutionincluding a copper sulfate solution, a sulfuric acid solution, and asolution including chlorine ions. Interconnect 40 is vertically grownfrom the exposed areas of the copper seed component of layer 35 towardand past the top of trench 20.

Referring to FIG. 2H, interconnect 40, hard mask 45, and liner and seedlayer 35 may be planarized so as to be coplanar with a top surface ofdielectric layer 25. In an embodiment, the planarization step may beperformed using chemical-mechanical polishing resulting in interconnect40 having a thickness of approximately 5 μm to approximately 20 μm and awidth of approximately 5 μm to approximately 150 μm. An example ofinterconnect 40 is a copper inductor or a transmission line.

An embodiment of an inductor is presented in accordance with the presentinvention. Referring to FIG. 3, an inductor 100 is provided having acore conductor 110, a trench 115, a dielectric layer 120, a substrate125, a liner and seed layer 130, and a hard mask 135.

Core conductor 110 includes a top surface 140, a bottom surface 145, andsidewalls 150 within trench 115. Core conductor 110 may comprise copper,silver, and gold, and may be approximately 5 microns (μm) toapproximately 150 μm wide and approximately 5 μm to approximately 20 μmdeep. Trench 115 is within dielectric layer 120 which is disposed onsubstrate 125. Substrate 125 may be a semiconductor substrate comprisingmaterials and including embodiments already described herein forsubstrate 30.

Dielectric layer 120 may be silicon dioxide (SiO₂) approximately 5 μm toapproximately 20 μm thick. In another example, dielectric layer 120 maybe fluorinated silicon dioxide (FSG) or an organic material, forexample, polyimide. Examples of materials for use as dielectric layer120 are known in the art. Additionally, dielectric layer 120 may be adual layer or a stack of three dielectric layers wherein adjacent layerscomprise different dielectric materials.

Trench 115 may be approximately 5 μm to approximately 150 μm wide andapproximately 5 μm to approximately 20 μm deep. Trench 115 may beconformally coated with liner and seed layer 130. Embodiments of linerand seed layer 130 are the same as for liner and seed layer 35 describedherein for FIG. 2B.

Core conductor 110 includes hard mask 135 on sidewalls 150. Hard mask135 may be an anti-seeding material or a dielectric material. Theanti-seeding conductive material may be selected from the groupconsisting of TiN, W, Ta, and TaN. The dielectric material may beselected from the group consisting of silicon nitride (Si₃N₄), siliconcarbide (SiC).

An embodiment of steps of a method of fabricating an inductor are shownin FIGS. 4A-4H. Referring to FIG. 4A, a substrate 125 comprisingsilicon, silicon-on-insulator, silicon germanium, or gallium arsenide isprovided. Substrate 125 may include any construction comprisingsemiconductor material, including but not limited to bulksemi-conductive materials such as a semiconductor wafer (either alone orin assemblies comprising other materials thereon). Substrate 125 mayalso be a semiconductor substrate comprising materials and includingembodiments already described herein for substrate 30.

Substrate 125 may already have dielectric layer 120 deposited thereon.In an embodiment, dielectric layer 120 may be silicon dioxide.Alternatively, dielectric layer 120 may be deposited on substrate 125using any now known or later developed techniques appropriate for thematerial to be deposited. Examples of such techniques have beendescribed herein in the description for FIG. 2A

Trench 115 is etched into dielectric layer 120. This may be accomplishedby applying a layer of photoresist to dielectric layer 120, performing aphotolithographic process, and performing a reactive ion etch (RIE)process selective to etch, for example, silicon dioxide, to definetrench 115 in dielectric layer 120.

Referring to FIG. 4B, trench 115 may be conformally coated with a linerand seed layer 130. The liner component of layer 130 deposited may be Taapproximately 100 Å to approximately 1,000 Å thick. The seed componentof layer 130 may be copper metal 400 Å to approximately 2,000 Å thick.In an embodiment, the liner component may contact dielectric layer 120and substrate 125 with the seed component overlaying the linercomponent. The aforementioned may be formed by PVD. Liner and seed layer130 may conformally coat the bottom and side walls of trench 115, andtop surface of dielectric layer 120.

Referring to FIG. 4C, hard mask 135 may be deposited on liner and seedlayer 130 via conventional CVD or PVD processes known in the art.Alternatively, hard mask 135 may be deposited using the techniquesdescribed herein for FIG. 3C. Hard mask 135 may comprise TiN and may beapproximately 300 Å to approximately 1,000 Å thick throughout the entirelayer. In an embodiment, hard mask 135 may be approximately 400 Å thick.

Referring to FIG. 4D, trench 115 may be masked with a photoresist layer155 and patterned to expose the area of hard mask 135 that coats thebottom of trench 115. Photoresist layer 155 may be approximately 5 μm toapproximately 50 μm thick. In one embodiment, photoresist layer 155 maybe approximately 10 μm thick. Photoresist materials used for masking andpatterning, and the methods for performing the same are known in theart.

Referring to FIG. 4E, a reactive ion etch (RIE) may then be performedpartially etching the area of hard mask 135 that coats the bottom oftrench 115. The thickness of the partially etched area may further beetched to approximately 100 Å. The photoresist layer 155 may thensubsequently stripped.

Referring to FIG. 4F, a blanket RIE may be performed etching theremaining area of hard mask 135 that coats the bottom of trench 115 andthe areas of hard mask 135 coating liner and seed layer 130 ondielectric layer 120. The remaining area of hard mask 135 may be etchedaway exposing the copper seed component of layer 130, and the areascoating liner and seed layer 130 may then be etched to approximately 300Å.

Referring to FIG. 4G, core conductor 110 may be formed from liner andseed layer 130 by performing an electrolytic metal plating process tofill trench 115. The process may be performed with a current density ofapproximately 1 A/cm² to approximately 15 A/cm² using a plating solutionincluding a copper sulfate solution, a sulfuric acid solution, and asolution including chlorine ions. Core conductor 110 may be verticallygrown from the exposed areas of the copper seed component of layer 130toward and past the top of trench 115.

Referring to FIG. 4H, core conductor 110, hard mask 135, and liner andseed layer 130 are planarized so as to be coplanar with a top surface ofdielectric layer 120 so as to form inductor 100. In an embodiment, theplanarization step may be performed using chemical-mechanical polishingresulting in core conductor 110 having a thickness of approximately 5 μmto approximately 20 μm and a width of approximately 5 μm toapproximately 150 μm.

The terms “first,” “second,” and the like, herein do not denote anyorder, quantity, or importance, but rather are used to distinguish oneelement from another, and the terms “a” and “an” herein do not denote alimitation of quantity, but rather denote the presence of at least oneof the referenced item. The modifier “approximately” used in connectionwith a quantity is inclusive of the stated value and has the meaningdictated by the context, (e.g., includes the degree of error associatedwith measurement of the particular quantity). The suffix “(s)” as usedherein is intended to include both the singular and the plural of theterm that it modifies, thereby including one or more of that term (e.g.,the metal(s) includes one or more metals). Ranges disclosed herein areinclusive and independently combinable (e.g., ranges of “up toapproximately 25 wt %, or, more specifically, approximately 5 wt % toapproximately 20 wt %”, is inclusive of the endpoints and allintermediate values of the ranges of “approximately 5 wt % toapproximately 25 wt %,” etc).

The foregoing description of various aspects of the disclosure has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the disclosure to the precise formdisclosed, and obviously, many modifications and variations arepossible. Such modifications and variations that may be apparent to aperson skilled in the art are intended to be included within the scopeof the disclosure as defined by the accompanying claims.

1. An integrated circuit comprising: at least one trench within adielectric layer disposed on a substrate, the trench conformally coatedwith a liner and seed layer; and an interconnect within the trench, theinterconnect including a hard mask on sidewalls of the interconnect. 2.The integrated circuit according to claim 1, wherein the hard maskcomprises an anti-seeding conductive material selected from one oftitanium nitride (TiN), tungsten (W), tantalum (Ta), and tantalumnitride (TaN).
 3. The integrated circuit according to claim 1, whereinthe hard mask comprises a dielectric material selected from one ofsilicon nitride (Si₃N₄), silicon carbide (SiC), and aluminum oxide(Al₂O₃).
 4. The integrated circuit according to claim 1, wherein theinterconnect comprises a material selected from one of copper, silver,and gold.
 5. The integrated circuit according to claim 1, wherein theinterconnect is approximately 5 microns (μm) to approximately 150 μm anwide.
 6. The integrated circuit according to claim 1, wherein theinterconnect is an inductor or a transmission line.
 7. A method offabricating an interconnect in an integrated circuit, the methodcomprising: conformally coating a trench with a liner and seed layer,the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer; masking andpatterning the trench to expose the hard mask; removing exposed areas ofthe hard mask to expose areas of the liner and seed layer; electrolyticmetal plating the exposed areas of the liner and seed layer to form aninterconnect; and planarizing the interconnect with a top surface of thetrench.
 8. The method of fabricating an interconnect according to claim7, wherein the hard mask comprises a material selected from one oftitanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride(TaN), silicon nitride (Si₃N₄), silicon carbide (SiC) and aluminum oxide(Al₂O₃).
 9. The method of fabricating an interconnect according to claim7, wherein the interconnect comprises a material selected from one ofcopper, silver, and gold.
 10. The method of fabricating an interconnectaccording to claim 7, wherein the interconnect is approximately 5microns (μm) to approximately 150 μm wide.
 11. The method of fabricatingan interconnect according to claim 7, wherein the planarizing stepincludes chemical-mechanical polishing the interconnect.
 12. The methodof fabricating an interconnect according to claim 7, wherein theremoving step includes plasma etching one or more times the exposedareas of the liner and seed layer.
 13. The method of fabricating aninterconnect according to claim 7, wherein the electrolytic metalplating step includes plating the exposed areas of the liner and seedlayer with a current density of approximately 1 A/cm² to approximately15 A/cm² using a plating solution comprising a copper sulfate solution,a sulfuric acid solution, and a solution including chlorine ions.
 14. Aninductor comprising: a core conductor including a top surface, a bottomsurface, and sidewalls within a trench, the trench being within adielectric layer on a substrate, and the trench having a liner and seedlayer on a bottom and sidewalls of the trench; and a hard mask on thesidewalls of the core conductor.
 15. The inductor according to claim 14,wherein the core conductor comprises a material selected from one ofcopper, silver, and gold.
 16. The inductor according to claim 14,wherein the core conductor is approximately 15 microns (μm) toapproximately 150 μm wide.
 17. The inductor according to claim 14,wherein the hard mask comprises an anti-seeding conductive materialselected from one of titanium nitride (TiN), tungsten (W), tantalum(Ta), and tantalum nitride (TaN).
 18. The inductor according to claim14, wherein the hard mask comprises a dielectric material selected fromone of silicon nitride (Si₃N₄), silicon carbide (SiC), and aluminumoxide (Al₂O₃).
 19. A method of fabricating an inductor, the methodcomprising: conformally coating a trench with a liner and seed layer,the trench being within a dielectric layer on a substrate; depositing ahard mask on the liner and seed layer; masking and patterning the trenchto expose the hard mask; removing exposed areas of the hard mask toexpose areas of the liner and seed layer; electrolytic metal plating theexposed areas of the liner and seed layer to form a core conductor; andplanarizing the core conductor, the hard mask, and the liner and seedlayer with a top surface of the trench.
 20. The method of fabricating aninductor according to claim 19, wherein the hard mask comprises amaterial selected from one of titanium nitride (TiN), tungsten (W),tantalum (Ta), tantalum nitride (TaN), silicon nitride (Si₃N₄), siliconcarbide (SiC), aluminum oxide (Al₂O₃).
 21. The method of fabricating aninductor according to claim 19, wherein the core conductor comprises amaterial selected from one of copper, gold, and silver.
 22. The methodof fabricating an inductor according to claim 19, wherein theinterconnect is approximately 5 microns (μm) to approximately 150 μmwide.
 23. The method of fabricating an inductor according to claim 19,wherein the planarizing step includes chemical-mechanical polishing thecore conductor, the hard mask, and the liner and seed layer with a topsurface of the trench.
 24. The method of fabricating an inductoraccording to claim 19, wherein the removing step includes plasma etchingone or more times the exposed areas of the hard mask.
 25. The method offabricating an inductor according to claim 19, wherein the electrolyticmetal plating step includes plating the exposed areas of the liner andseed layer with a current density of approximately 1 A/cm² toapproximately 15 A/cm² using a plating solution comprising a coppersulfate solution, a sulfuric acid solution, and a solution includingchlorine ions.